CMOS device structures and method of making same
US6303450A · kind A · utility
37Cited by
8References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2000 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Nov 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6741
Abstract
Disclosed is a method comprising providing a silicon surface with an underlying insulator layer, providing a plurality of gates adjacent to source/drain regions, growing source/drains between the said gates such that the source/drains are thicker in regions of larger gate-to-gate pitch, and doping the source/drains with one or more dopants such that the dopants abut the underlying insulator layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.