Method and structure for reducing interconnect system capacitance through enclosed voids in a dielectric layer
US6303464A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1996 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Dec 30, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A reduced capacitance interconnect system. A first metal layer is formed to a predetermined level above a first dielectric layer which is formed on a semiconductor substrate. The first metal layer level forms multiple interconnect lines wherein each interconnect line is separated from each adjacent interconnect line by a trench including a trench having a highest aspect ratio. A second dielectric layer is formed on the first metal layer and in the trenches between the interconnect lines such that an enclosed void having a void tip substantially level with the top of the metal layer is formed in at least each trench having an aspect ratio above a predetermined minimum aspect ratio, wherein the enclosed void in the trench having the highest aspect ratio has a void volume which is at least 15% of the volume of the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.