Semiconductor integrated circuit device and method for fabricating the same
US6303478A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1999 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Oct 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device having, for example, a memory cell array portion and a peripheral circuit portion is disclosed. By such a method, a first interlayer insulating film is formed on a semiconductor substrate, a first connection hole is formed by selectively removing a predetermined portion of the first interlayer insulating film, the sides of the first hole being substantially vertical to the bottom thereof, a first plug is formed by padding the first hole with a metallic film and, subsequently, a second interlayer insulating film is formed on the first insulating film, a second hole is formed by selectively removing a predetermined portion of the second interlayer insulating film, the sides of the second hole being substantially vertical to the bottom thereof, and a second plug aligned to be in direct connection with the first plug is formed by padding the second hole with the metallic film. A MOS transistor is formed on the semiconductor substrate before the first interlayer insulating film is formed and the first hole formed is extended to expose the diffused layer of the MOS transistor. The surfaces of both the first and second interlayer insulating f…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.