Layout for a semiconductor memory
US6304478A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 14, 2000 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Jul 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention pertains to a layout for a semiconductor memory with multiple memory cells. The layout according to this invention takes into account the "design rules" specified by the manufacturing process or those required by the technology, and attempts to optimize the surface area of the layout of the semiconductor memory. The particular advantage of the invention rests in the fact that for each memory cell, effectively only one contact terminal is needed. In this manner, the required surface area for the semiconductor memory can be reduced significantly. Due to the reduction in the number of contact terminals, the leakage currents can also be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.