Double layer hard mask process to improve oxide quality for non-volatile flash memory products

US6306707A · kind A · utility

Assignee

• ADANCED MICRO DEVICES, INC. · US

Inventors

• John Foster · Mountain View, US
• Yue-Song He · San Jose, US
• Jiahua Huang · San Jose, US

Key dates

• Filing date: Nov 20, 2000
• Grant date: Oct 23, 2001
• Expiry date: Nov 20, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

In the manufacture of an EPROM or EEPROM semiconductor device that includes a core region and a peripheral region, a nitride layer is formed over the core region and peripheral region, and an oxide layer is formed over the nitride layer. A layer of photoresist is provided over the oxide layer and is patterned to expose a portion of the oxide layer overlying the core region. A wet etch step is undertaken to remove the exposed portion of the oxide layer, using the patterned photoresist as a mask, and leaving exposed a portion of the nitride layer overlying the core region. After removal of the photoresist, the exposed portion of the nitride layer is etched by a wet etch step with hot phosphoric acid, using the pattered oxide layer as a mask.