Low-consumption TTL-CMOS input buffer stage
US6307396A · kind A · utility
8Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1998 |
| Grant date | Oct 23, 2001 |
| Priority date | — |
| Expiry date | Dec 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low-consumption TTL-CMOS input buffer stage includes a chain of inverters cascade connected between an input receiving electric signals at a TTL logic level and an output reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a second or ground reference. Advantageously, the first inverter in the chain includes a means of selecting the delivery path to the stage according to an activate signal for a low-consumption operation mode. In essence, the first inverter of the buffer has two signal paths: one for normal operation and the other for low consumption operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.