Method and apparatus for realizable interconnect reduction for on-chip RC circuits
US6308304A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 1999 |
| Grant date | Oct 23, 2001 |
| Priority date | — |
| Expiry date | May 27, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Realizable interconnect reduction techniques for on-chip RC interconnects are disclosed by first partitioning the original circuit into sets of two-port circuits to maintain the spatial sparsity of the reduced model. Each original two-port circuit is matched to a reduced RC circuit having a specific configuration. The moments of the original two-port circuits are calculated. Closed form expression values of the reduced circuit elements are then calculated from the moments of the original circuits. The closed form expressions for calculating the values of the elements in the reduced circuit use a reduced number of independent variables associated with the elements, thus simplifying the calculations. An efficient linear time moment computation technique is used for computing the moments for the two-port circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.