Anirudh Devgan
29Patents
12h-index
23Co-inventors
77Inventor score
Filing activity: Sep 15, 1997 → Oct 29, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6117182A | Optimum buffer placement for noise avoidance | Physics | 213 | Expired |
| US6347393B1 | Method and apparatus for performing buffer insertion with accurate gate and interconnect delay computation | Physics | 212 | Expired |
| US7376001B2 | Row circuit ring oscillator method for evaluating memory cell performance | Physics | 66 | Expired |
| US7301835B2 | Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability | Physics | 59 | Expired |
| US6842714B1 | Method for determining the leakage power for an integrated circuit | Physics | 46 | Expired |
| US6029117A | coupled noise estimation method for on-chip interconnects | Physics | 31 | Expired |
| US7137080B2 | Method for determining and using leakage current sensitivities to optimize the design of an integrated circuit | Physics | 26 | Expired |
| US7000205B2 | Method, apparatus, and program for block-based static timing analysis with uncertainty | Physics | 21 | Expired |
| US6308304A | Method and apparatus for realizable interconnect reduction for on-chip RC circuits | Physics | 21 | Expired |
| US6662149B1 | Method and apparatus for efficient computation of moments in interconnect circuits | Physics | 21 | Expired |
| US6044209A | Method and system for segmenting wires prior to buffer insertion | Physics | 19 | Expired |
| US8572523B2 | Lithography aware leakage analysis | Physics | 17 | Active |
| US7304895B2 | Bitline variable methods and circuits for evaluating static memory cell dynamic stability | Physics | 11 | Active |
| US7036104B1 | Method of and system for buffer insertion, layer assignment, and wire sizing using wire codes | Physics | 9 | Expired |
| US7483322B2 | Ring oscillator row circuit for evaluating memory cell performance | Physics | 8 | Active |
| US8001493B2 | Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions | Physics | 7 | Active |
| US6434729B1 | Two moment RC delay metric for performance optimization | Physics | 6 | Expired |
| US7302661B2 | Efficient electromagnetic modeling of irregular metal planes | Physics | 3 | Expired |
| US7561483B2 | Internally asymmetric method for evaluating static memory cell dynamic stability | Physics | 3 | Active |
| US7434188B1 | Lithographically optimized placement tool | Physics | 2 | Expired |
| US6868533B2 | Method and system for extending delay and slew metrics to ramp inputs | Physics | 2 | Expired |
| US8473876B2 | Lithography aware timing analysis | Physics | 1 | Active |
| US7558136B2 | Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability | Physics | 1 | Active |
| US6950996B2 | Interconnect delay and slew metrics based on the lognormal distribution | Physics | 1 | Expired |
| US7827514B2 | Efficient electromagnetic modeling of irregular metal planes | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.