Test structures for testing planarization systems and methods for using same
US6309900A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2000 |
| Grant date | Oct 30, 2001 |
| Priority date | — |
| Expiry date | Jan 11, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Test structures are disclosed for use in a system and with an associated method to test the effectiveness of planarization systems used in the fabrication of semiconductor devices and integrated circuits. A method of creating the test structure utilizes traditional semiconductor fabrication techniques, but uses substantially similar materials, such as oxide, for each of the layers of the test structure. Because the test structure comprises layers of substantially the same material, reliable uniform measurements of the thickness of the test structure may be obtained by an optical metrology tool. These measurements may then be analyzed and displayed in tabular reports or multi-dimensional plots to judge the effectiveness of the planarization system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.