Manufacturable GaAs VFET process

US6309918A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Jenn Hwa Huang · Chandler, US
• Benjamin W. Gable · Chandler, US
• Kurt Eisenbeiser · Tempe, US
• David Rhine · Georgetown, US

Key dates

• Filing date: Sep 21, 1998
• Grant date: Oct 30, 2001
• Expiry date: Sep 21, 2018

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/945

Abstract

A manufacturable GaAs VFET process includes providing a doped GaAs substrate with a lightly doped first epitaxial layer thereon and a heavily doped second epitaxial layer positioned on the first epitaxial layer. A temperature tolerant conductive layer is positioned on the second epitaxial layer and patterned to define a plurality of elongated, spaced apart source areas. Using the patterned conductive layer, a plurality of gate trenches are etched into the first epitaxial layer adjacent the source areas. The bottoms of the gate trenches are implanted and activated to form gate areas. A gate contact is deposited in communication with the implanted gate areas, a source contact is deposited in communication with the patterned conductive layer overlying the source areas, and a drain contact is deposited on the rear surface of the substrate.