SRAM cell arrangement and method for manufacturing same

US6309930A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Bernd Goebel · Dresden, DE
• Emmerich Bertagnolli · Munich, DE
• Josef Willer · Riemerling, DE
• Barbara Hasler · Munich, DE
• Paul-Werner von Basse · Wolfratshausen, DE

Key dates

• Filing date: Nov 9, 2000
• Grant date: Oct 30, 2001
• Expiry date: Nov 9, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/12

Abstract

The SRAM cell arrangement comprises six MOS transistors per memory cell that are fashioned as vertical transistors. The MOS transistors are arranged at sidewalls of trenches (G1, G2, G4). Parts of the memory cell such as, for example, gate electrodes (Ga2, Ga4) or conductive structures (L3) fashioned as spacer are contacted via adjacent, horizontal, conductive structures (H5) arranged above a surface (O) of a substrate (S). Connections between parts of memory cells ensue via third conductive structures (L3) arranged at the sidewalls of the depressions and word lines (W) via diffusion regions (D2) that are adjacent to the sidewalls of the depressions within the substrate (S), via first bit lines, via second bit lines (B2) or/and via conductive structures (L1, L2, L6) that are partially arranged at different height with respect to an axis perpendicular to the surface (O). Contacts (K5) contact a plurality of parts of the MOS transistors simultaneously.