Method of low-K/copper dual damascene
US6309957A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2000 |
| Grant date | Oct 30, 2001 |
| Priority date | — |
| Expiry date | Apr 3, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1026
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to both dual and single inverse copper damascene processes to form conducting copper interconnects and contact vias simultaneously, with low dielectric constant intermetal dielectrics (IMD). The low dielectric constant material, low-K, can be of four types of material: doped oxide, organic materials, highly fluorinated films, porous materials. In addition, spin-on glass (SOG) and spin-on-dielectric (SOD) are applicable. Key to the present invention are the following process steps, that have exceptionally advanced process controls: polysilicon etching of sacrificial polysilicon, plasma ashing of the patterning photoresist, and post cleaning. With conventional dual damascene, wherein dielectric material is patterned into dual damascene, several deleterious effects occur: (1) etching of low-K material can be difficult and can affect the electrical properties, (2) photoresist ashing can impact both the dielectric constant of low-K material and critical dimensional bias control, (3) post cleaning can impact the dielectric constant of low-K material. Using both the i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.