MOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layer
US6310367A · kind A · utility
139Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2000 |
| Grant date | Oct 30, 2001 |
| Priority date | — |
| Expiry date | Feb 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device in which an NMOSFET and a PMOSFET are formed in a silicon substrate, wherein the gate electrodes of NMOSFET and PMOSFET are made of metallic materials, an Si--Ge layer is formed in at least part of the surface regions including the respective channel layers of the NMOSFET and PMOSFET, and the concentration of Ge in the channel layer of the NMOSFET is lower than the concentration of Ge in the channel layer of the PMOSFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.