Generator scheme and circuit for overcoming resistive voltage drop on power supply circuits on chips
US6310511A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 16, 2000 |
| Grant date | Oct 30, 2001 |
| Priority date | — |
| Expiry date | Jun 16, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/242
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
Apparatus is used to dynamically control the power output of generators of a generator system on a chip to load circuits on the chip. A power bus is directed along at least one "spine" section on the chip which may intersect with at least one "arm" section on the chip for supplying power from the generators, which are coupled to the power bus in the "spine" section thereof, to circuits on the chip. The power bus has a feedback lead from each end which is remote from the generators for providing a continuous measurement of a voltage drop occurring at each remote end. At least one detector circuit is located at a predetermined point adjacent the generators of the chip for comparing a voltage from the generators measured at the predetermined point with the concurrent voltage drop measured at an associated remote end. In response to such comparison, the at least one detector circuit generates control signals for transmission to the generators for altering a generated voltage to maintain a predetermined power level on the power bus in response to load changes caused by the circuits on the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.