Rambus DRAM (RDRAM) apparatus and method for performing refresh operations
US6310814A · kind A · utility
126Cited by
7References
40Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 8, 2000 |
| Grant date | Oct 30, 2001 |
| Priority date | — |
| Expiry date | Aug 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for concurrently refreshing first and second rows of memory cells in a dynamic random access memory (DRAM) component that includes a plurality of banks of memory cells organized in rows. A command interface in the DRAM component receives activate requests and precharge requests. A row register in the DRAM component indicates a row in the DRAM component. Logic in the DRAM component activates the row indicated by the row register in response to an activate request and precharges the row in response to a precharge request, the row being in a bank indicated by the activate request and by the precharge request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.