System and method for testing a clock signal
US6311295A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1996 |
| Grant date | Oct 30, 2001 |
| Priority date | — |
| Expiry date | Jun 14, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/30
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention utilizes a test circuit for receiving a reference clock signal and a sense clock signal and subsequently determining whether or not the reference and sense clock signals are either correct multiples of each other and/or in phase with each other. The test circuit may be located on the same chip with the microprocessor and the clock circuitry. The clock circuitry may include a phase locked loop ("PLL") circuit for receiving the reference clock signal and producing a sense clock signal for use by the remainder of the chip, wherein the sense clock signal is a multiple of the reference clock signal. The test circuit may count the number of cycles of the sense clock signal occurring within a predetermined amount of time, which may be proportional to the reference clock period. Alternatively, the sense clock signal and the reference clock signal may be passed through an XOR circuit and then the number of cycles counted within a predetermined time period. In both cases, if the number of cycles counted is not what was expected, then it is known that the sense clock signal was not properly produced by the PLL circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.