Semiconductor package and method of manufacturing the same
US6312975A · kind A · utility
5Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1999 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Jan 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package having an encapsulation that encapsulates an integrated circuit chip and an external lead frame for the chip. Multiple connection leads project from the periphery of the encapsulation. At least one external face of the encapsulation is covered with a layer of electrically conductive material, and the conducting material layer has at least one lateral extension that electrically contacts at least one of the projecting connection leads. A method of manufacturing such a semiconductor package is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.