Etching method for reducing bit line coupling in a DRAM
US6312983A · kind A · utility
4Cited by
5References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1999 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Oct 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76804
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a bit line of a DRAM memory array is disclosed. The method comprises the steps of: forming an interlayer dielectric over the DRAM memory array; etching the interlayer dielectric to form trenches in the interlayer dielectric, the trenches collectively forming a bit line pattern and having tapered side walls; and depositing a conductive material into the trenches to form the bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.