Promos Technologies, Inc.
345Patents
66Active
345Granted
45Portfolio score
Filing activity: Jun 9, 1998 → Apr 5, 2011 · 65 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6855610B2 | Method of forming self-aligned contact structure with locally etched gate conductive layer | Electricity | 211 | Expired |
| US6429148B1 | Anisotropic formation process of oxide layers for vertical transistors | Electricity | 77 | Expired |
| US7061823B2 | Limited output address register technique providing selectively variable write latency in DDR2 (double data rate two) integrated circuit memory devices | Physics | 74 | Expired |
| US7122415B2 | Atomic layer deposition of interpoly oxides in a non-volatile memory device | Electricity | 54 | Expired |
| US6526996B1 | Dry clean method instead of traditional wet clean after metal etch | Emerging Cross-Sectional Technologies | 53 | Expired |
| US6632742B2 | Method for avoiding defects produced in the CMP process | Electricity | 50 | Expired |
| US6885044B2 | Arrays of nonvolatile memory cells wherein each cell has two conductive floating gates | Emerging Cross-Sectional Technologies | 40 | Expired |
| US6123865A | Method for improving etch uniformity during a wet etching process | Electricity | 33 | Expired |
| US6432728B1 | Method for integration optimization by chemical mechanical planarization end-pointing technique | Electricity | 33 | Expired |
| US6703273B2 | Aggressive capacitor array cell layout for narrow diameter DRAM trench capacitor structures via SOI technology | Electricity | 31 | Expired |
| US7910429B2 | Method of forming ONO-type sidewall with reduced bird's beak | Electricity | 29 | Expired |
| US6511905B1 | Semiconductor device with Si-Ge layer-containing low resistance, tunable contact | Electricity | 28 | Expired |
| US6507800B1 | Method for testing semiconductor wafers | Electricity | 27 | Expired |
| US7018895B2 | Nonvolatile memory cell with multiple floating gates formed after the select gate | Physics | 26 | Expired |
| US6605535B1 | Method of filling trenches using vapor-liquid-solid mechanism | Emerging Cross-Sectional Technologies | 25 | Expired |
| US6818515B1 | Method for fabricating semiconductor device with loop line pattern structure | Electricity | 24 | Expired |
| US7679163B2 | Phase-change memory element | Electricity | 22 | Active |
| US6521956B1 | Semiconductor device having contact of Si-Ge combined with cobalt silicide | Electricity | 21 | Expired |
| US6143653A | Method of forming tungsten interconnect with tungsten oxidation to prevent tungsten loss | Electricity | 21 | Expired |
| US7660147B2 | Programming method for phase change memory | Physics | 21 | Active |
| US6399461B1 | Addition of planarizing dielectric layer to reduce a dishing phenomena experienced during a chemical mechanical procedure used in the formation of shallow trench isolation regions | Electricity | 20 | Expired |
| US6391705B1 | Fabrication method of high-density semiconductor memory cell structure having a trench | Electricity | 20 | Expired |
| US6838342B1 | Nonvolatile memory fabrication methods comprising lateral recessing of dielectric sidewalls at substrate isolation regions | Electricity | 19 | Expired |
| US6393210B1 | Rapid thermal processing method and apparatus | Electricity | 18 | Expired |
| US6701204B1 | System and method for finding defective tools in a semiconductor fabrication facility | Electricity | 17 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.