Method for suppressing narrow width effects in CMOS technology
US6313011A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 28, 1999 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Oct 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76232
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an example embodiment, a method for manufacturing a semiconductor device having shallow trench isolation comprises forming a trench region in a substrate having a substantially planar bottom, a first and second sidewall. In the trench region, the method forms a dielectric liner on the bottom and the first and second sidewalls. The dielectric liner is a silicon nitride compound. The dielectric liner minimizes the anomalous increases in threshold voltage with width (V.sub.t versus W) owing to transient enhanced up-diffusion of the channel profile induced by source/drain implant damage. In addition, the anomalous increase in V.sub.t versus W associated with the formation of an interstitial gradient in sub-micron devices is reduced. By using a nitrided liner, V.sub.t roll off due to boron segregation is also minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.