Floating gate transistor having buried strained silicon germanium channel layer

US6313486A · kind A · utility

Assignee

• The Board of Regents of the University of Texas System · US

Inventors

• David L. Kencke · Beaverton, US
• Sanjay Banerjee · Austin, US

Key dates

• Filing date: Jun 15, 2000
• Grant date: Nov 6, 2001
• Expiry date: Jun 15, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/685

Abstract

A field effect transistor such as a flash EEPROM device has channel region between a source region and a drain region with the channel region including a silicon germanium alloy layer epitaxially grown on a silicon substrate and a silicon cap layer epitaxially grown on the alloy layer. A floating gate is provided over and insulated from the channel region, and a control gate is provided over and insulated from the floating gate. The silicon germanium alloy layer and cap silicon layer provide for enhanced secondary impact ionization when injecting electrons from the channel region into the floating gate in programming the device. In a preferred embodiment the SiGe alloy layer is graded with the germanium mole fraction increasing from zero to some maximum value in the growth direction and with the germanium layer thickness being below a critical thickness for maintaining pseudomorphic strain.