Vertical channel floating gate transistor having silicon germanium channel layer

US6313487A · kind A · utility

Assignee

• The Board of Regents of the University of Texas System · US

Inventors

• David L. Kencke · Beaverton, US
• Sanjay Banerjee · Austin, US

Key dates

• Filing date: Jun 15, 2000
• Grant date: Nov 6, 2001
• Expiry date: Jun 15, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6891

Abstract

A vertical channel flash memory cell with a silicon germanium layer in the channel region provides enhanced secondary electron injection when programming the device. The device includes a silicon substrate, a silicon germanium alloy layer epitaxially grown on the substrate, and a silicon layer epitaxially grown on the silicon germanium layer. A sidewall through the stacked structure is formed by etching thereby exposing edges of the silicon layer and the silicon germanium layer and a portion of the substrate. A floating gate is formed overlying the sidewall and insulated therefrom with a control gate overlying the floating gate and insulated therefrom. A source region is formed in the silicon layer and a drain region is formed in the substrate with a channel therebetween along the sidewall and including the silicon germanium layer. The silicon germanium layer is preferably compressively strained and can have a uniform mole fraction or a graded mole fraction. The vertical structure permits the fabrication of flash memory cells with smaller dimensions and lower operating voltages.