Split gate memory cell

US6313500A · kind A · utility

Assignee

• Agere Systems Guardian Corporation · US

Inventors

• Patrick J. Kelley · Orlando, US
• Chung Wai Leung · Orlando, US
• Ranbir Singh · Cary, US

Key dates

• Filing date: Dec 14, 1999
• Grant date: Nov 6, 2001
• Expiry date: Dec 14, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A split gate memory cell is described which is fabricated from two-polysilicon layers and comprises a silicon substrate having a source and a drain electrode and a storage node, a tunnel oxide on the substrate, a first control gate electrode and a floating gate electrode spaced from each other and fabricated from the same polysilicon layer and a second control gate electrode of a second poly material formed between and over the first control gate and floating gate and isolated therefrom by a dielectric layer therebetween.