Delta-sigma analog-to-digital converter, and method
US6313774A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2000 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | May 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/412
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter (200) has a first stage (207) to integrate and quantize the difference between a feedback signal (R) and an input signal (X) to a first intermediate signal (Y.sub.1) with a first resolution (M.sub.1), a second stage (208) to integrate and quantize the first intermediate signal (Y.sub.1) to a second intermediate signal (Y.sub.2) with a second, lower resolution (M.sub.2), a feedback stage (260) to convert the second intermediate signal (Y.sub.2) to the feedback signal (R), and a third stage (206, 270, 280, 285) to differentiate the first intermediate signal (Y.sub.1) to a third intermediate signal (W.sub.1), to delay the second intermediate signal (Y.sub.2) to a fourth intermediate signal (W.sub.2), and to add the third and fourth intermediate signals (W.sub.1, W.sub.2) to an output signal (Y) having a resolution that results from the sum of the first (M.sub.1) and second (M.sub.2) resolutions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.