Nonvolatile semiconductor memory device and semiconductor integrated circuit
US6314021A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2000 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Nov 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
All source regions belonging to a row are electrically connected to one another through a silicon layer (4) in a portion between a bottom surface of a partial-isolation insulating film (5) and an upper surface of a BOX layer (3). These constitute source lines (SL1 to SL5) extending like strips in a row direction. The isolation insulating film (5) between the source regions adjacent to each other in the row direction is removed and in the silicon layer (4) of the portion exposed by removing the isolation insulating film (5), an impurity introduction region (10) having the same conductivity type as the source region has is formed. With this structure, a nonvolatile semiconductor memory device which causes no malfunction due to driving of a parasitic bipolar transistor can be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.