Memory device having write latency
US6314051A · kind A · utility
137Cited by
78References
43Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2000 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Jul 31, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device having a plurality of memory cells, the memory device comprising clock receiver circuitry to receive an external clock signal, and input receiver circuitry to sample, in response to a write request, a first portion of data after a number of clock cycles of the external clock signal transpire. The first portion of data is sampled synchronously with respect to the external clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.