Method for generating computer aided design programming circuit designs from scanned images of the design
US6314194A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 1995 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Jul 26, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A VHSIC hardware description language model is generated from a scanned image of an electronic circuit by: a. producing a bitmap image of a schematic using standard scanning devices that takes a paper drawing and produces an image of a drawing in electronic form where the white and black parts of the drawing image are represented by different values, for example, 0 representing white and 1 representing black; locating and identifying the text portions of the schematic which is used later to tag signal and pin names to reassemble hierarchical schematic drawing sets into models where the links between the various schematic drawings are included in the model; locating and identifying the drawing symbols, such as logic gates, transistors, and resistors, as well as the pins that link one schematic drawing to other schematics in a set of drawings, which is used to type each component in the schematic; locating and identifying the signals (or nets) which is a three stage process where the individual signal paths are located and identified, the inversion circles, which are critical to the correct identification of component function, are located and the ports (connections to signals) for e…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.