Peer-to-peer cache moves in a multiprocessor data processing system
US6314491A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 1999 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Mar 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cache system is used in a multiprocessor environment. The first processor accesses data using a first level 1 cache, and the second processor accesses data using a second level 1 cache. A storage control circuit is positioned between the first and second level 1 caches and a level 2 cache and main memory. The level 2 cache maintains copies of data in main storage and further maintains an indication of those level 1 caches having copies of data and whether those copies have been modified. When a processor accesses data that is not resident in the connected level 1 cache, a request is delivered to the level 2 cache for this data. The level 2 cache then determines whether it can return a copy of the data to the level 1 cache or must access the data from main memory. Also, when the level 2 cache determines that another level 1 cache is storing a modified copy of the data, the level 2 cache returns to the storage control circuit a pointer to the level 1 cache having the modified copy of the data; the storage control circuit then causes the level 1 cache having a modified copy of the data, to transfer the modified data to the requesting level 1 cache without returning the data t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.