Branch history cache
US6314493A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 3, 1998 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Feb 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a predictive instruction cache system, and the method it embodies, for a VLIW processor. The system comprises: a first cache; a real or virtual second cache for storing a subset of the instructions in the second cache; and a real or virtual history look-up table for storing relations between first instructions and second instructions in the second cache. If a first instruction is located in a stage of the pipeline, then one of the relations will predict that a second instruction will be needed in the same stage a predetermined time later. The first cache can be physically distinct from the second cache, but preferably is not, i.e., the second cache is a virtual array. The history look-up table can also be physically distinct from the first cache, but preferably is not, i.e., the history look-up table is a virtual look-up table. The first cache is organized as entries. Each entry has a first portion for the first instruction and a second portion for a branch-to address indicator pointing to the second instruction. For a given first instruction, a new branch-to address indicator independently can be stored in the second field to replace an old branch-to address indicator…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.