Circuit synthesis and verification using relative timing
US6314553A · kind A · utility
11Cited by
8References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 1998 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | Nov 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of synthesizing and/or verifying a circuit from a behavioral description of that circuit. A signal ordering of signals in the circuit is defined, wherein defining a signal ordering of signals in the circuit includes specifying a relative ordering of a plurality of events within the circuit. The behavioral description is modified as a function of the signal ordering. The circuit is then synthesized and/or verified as a function of the modified behavioral description.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.