Top layer imaging lithography for semiconductor processing
US6316168A · kind A · utility
9Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1999 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Apr 12, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S430/151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for etching a surface includes the steps of providing an under layer formed on the surface and a top layer formed on the under layer. The top layer is patterned to expose portions of the under layer, and a layer including silicon is formed on the exposed portions of the under layer. The top layer is removed to expose the under layer in portions other than the portions of the under layer having the silicon layer thereon, and the under layer is etched in portions other than the portions of the under layer having the silicon layer thereon to expose the surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.