Method of forming self-isolated and self-aligned 4F-square vertical FET-trench DRAM cells

US6316309A · kind A · utility

Inventors

• Steven J. Holmes · Colchester, US
• Howard L. Kalter · Colchester, US
• Sandip Tiwari · Ithaca, US
• Jeffrey J. Welser · Stamford, US

Key dates

• Filing date: Jul 26, 2000
• Grant date: Nov 13, 2001
• Expiry date: Jul 26, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/34

Abstract

A densely packed array of vertical semiconductor devices, having pillars, deep trench capacitors, vertical transistors, and methods of making thereof are disclosed. The pillars act as transistor channels, and may be formed utilizing the application of hybrid resist over a block of semiconductor material. Drain doped regions are formed on the top of each pillar. The source doped regions and the plate doped regions are self-aligned and are created by diffusion in the trenches surrounding the pillars. The array has columns of bitlines and rows of wordlines. The capacitors are formed by isolating n.sup.+ polysilicon in trenches separating said pillars. The array is suitable for GBit DRAM applications because the deep trench capacitors do not increase array area. The array may have an open bitline architecture, where the plate region is common to all the storage nodes or a folded architecture with two wordlines that pass through each cell having stacked transistors, where one wordline is active and the other is passing for each cell.