Method for fabricating an integrated circuit device
US6316358A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 1999 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Jul 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a uniform conductive pattern on an integrated circuit substrate having a step by a single photography process. An exposure mask has a different pattern in accordance with the topology of the integrated circuit substrate. The exposure mask has a increased inter-pattern space at a lower portion of the step and has a reduced inter-pattern space at a upper portion of the step. During the exposure process, a sufficient amount of light is applied to a photoresist layer at the lower portion of the step and an optical amount of light is applied to the photoresist layer at the upper portion of the step. As a result, scum phenomenon at the lower portion of the step can be prevented. Further, overetching of the conductive pattern at the upper portion of the step can be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.