Microprocessor having a prefetch cache
US6317810A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1997 |
| Grant date | Nov 13, 2001 |
| Priority date | — |
| Expiry date | Jun 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A central processing unit of a computer includes a single-ported data cache and a dual-ported prefetch cache. The data cache accommodates a first pipeline and the prefetch cache, which is much smaller than the data cache, accommodates both the first pipeline and a second pipeline. If a data cache miss occurs, a row of data corresponding to the specified address is stored in the data cache and the prefetch cache. Thereafter, if a prefetch cache hit occurs, a row of data corresponding to a prefetch address is loaded into the prefetch cache. The prefetch address may, for instance, be generated by adding a fixed increment to the specified address. This operation frequently results in the prefetch cache storing data soon requested by a computer program. When this condition is achieved, the data corresponding to the subsequent address request is rapidly retrieved from cache memory without incurring memory latencies associated with the external cache, the primary memory, and the secondary memory. In this manner, the prefetch cache of the present invention facilitates improved memory latencies. Further, the prefetch cache allows for two data requests to be processed simultaneously without …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.