Method for fabricating a memory device with a high dielectric capacitor
US6319765A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1999 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Dec 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
The present invention provides a method for fabricating a ferroelectric memory device to reduce manufacturing cost and to obtain the electric characteristic of capacitor. The method comprises the steps of: forming an intermetal insulating layer provided with a contact hole exposing a junction region formed on a semiconductor layer having the junction region; forming a contact plug within the contact hole; forming a barrier layer and a metal layer for lower electrode on the intermetal insulating layer successively; forming a lower electrode by patterning selected portions of the metal layer for lower electrode and the barrier layer; forming a high dielectric layer on the substrate on which the lower electrode is formed; and forming an upper electrode on the high dielectric layer, wherein during forming the upper electrode, an F ion layer to be trapped by dangling bonds formed at an interface between the upper electrode and the high dielectric layer, is formed at the interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.