Electric wiring forming method with use of embedding material
US6319815A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 1999 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Oct 18, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76801
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a wiring structure on a semiconductor substrate, comprising the following steps: a step for forming a low dielectric constant dielectric film and an etching stopper, sequentially, on said semiconductor substrate; a step for forming a resist mask having a pattern for forming via-holes on the etching stopper film; a step for forming via-holes on the low dielectric constant dielectric film through said resist mask; a step for filling said via-holes with an embedding material and for heating the embedding material to harden; a step for maintaining the embedding material at a predetermined thickness on the bottoms of the via-holes by performing etching back on the embedding material being heated to be harden; a step for forming a resist mask having a pattern for forming trench holes on said etching stopper film; a step for forming the trench holes on said low dielectric film constant dielectric through said resist mask, while removing the embedding material remaining on the bottoms of said via-holes; and a step for embedding metal into said trench holes and said via-holes, wherein the embedding material mainly includes a thermo-bridge forming compound therein, there…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.