Method and structure for reducing the incidence of voiding in an underfill layer of an electronic component package
US6320127A · kind A · utility
11Cited by
3References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1999 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Dec 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10253
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging substrate includes a plurality of bonding pads and a plurality of gutters formed thereon. A die having conductive bumps on an electrically active surface thereof is positioned such that the conductive bumps of the die are electrically connected to the bonding pads of the packaging substrate. An underfill material fills the underfill space between the packaging substrate and the die to complete the structure. The plurality of gutters creates a linear flow front of the underfill material as it flows across the underfill space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.