Integrated circuit device having dual damascene capacitor
US6320244A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1999 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Sep 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes a dielectric layer having an opening therein, and a capacitor comprising in stacked relation a lower electrode lining the opening, a capacitor dielectric layer adjacent the lower electrode, and an upper electrode adjacent the capacitor dielectric layer. The capacitor has a substantially planar upper surface substantially flush with adjacent upper surface portions of the dielectric layer. Additionally, the edges of the lower electrode and the capacitor dielectric layer preferably terminate at the upper surface of the capacitor. Also, the capacitor dielectric may include a high-k, high quality and low leakage dielectric, and which prevents the reduction of the capacitor dielectric by the metal of the upper and lower metal electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.