Buffer device with dual supply voltage for low supply voltage applications
US6320361A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2000 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Dec 13, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/242
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.