Pseudo-static leakage-tolerant register file bit-cell circuit
US6320795A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2000 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Dec 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A register file for use within, for example, a microprocessor or other digital processing device includes a register file cell having a pull down transistor that is driven by a static logic circuit (e.g., a NOR gate). During a read operation, the static logic circuit causes the pull down transistor to discharge a dynamic bit line node when a predetermined data value is stored within a data storage area of the register file cell. The logic circuit serves to isolate the input terminal of the pull down transistor from a potentially noisy read signal received by the register file cell, thus preventing noise induced leakage currents from being created. In one embodiment, a bias circuit is provided that applies a bias signal to the pull down transistor during non-read intervals to significantly reduce leakage currents flowing through the pull down transistor at these times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.