Ram Krishnamurthy
189Patents
17h-index
129Co-inventors
89Inventor score
Filing activity: Dec 31, 1997 → Aug 24, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9104474B2 | Variable precision floating point multiply-add circuit | Physics | 68 | Active |
| US6204696A | Domino circuits with high performance and high noise immunity | Electricity | 34 | Expired |
| US6366061B1 | Multiple power supply circuit architecture | Physics | 30 | Expired |
| US6181166A | Tristate driver for integrated circuit interconnects | Electricity | 28 | Expired |
| US6271713A | Dynamic threshold source follower voltage driver circuit | Electricity | 28 | Expired |
| US6404237B1 | Boosted multiplexer transmission gate | Electricity | 28 | Expired |
| US6707708B1 | Static random access memory with symmetric leakage-compensated bit line | Physics | 25 | Expired |
| US6137319A | Reference-free single ended clocked sense amplifier circuit | Electricity | 23 | Expired |
| US7332937B2 | Dynamic logic with adaptive keeper | Electricity | 22 | Expired |
| US6633190B1 | Multi-phase clock generation and synchronization | Electricity | 21 | Expired |
| US6549040B1 | Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates | Electricity | 21 | Expired |
| US6563357B1 | Level converting latch | Electricity | 20 | Expired |
| US5986473A | Differential, mixed swing, tristate driver circuit for high performance and low power on-chip interconnects | Electricity | 19 | Expired |
| US6690604B2 | Register files and caches with digital sub-threshold leakage current calibration | Physics | 19 | Expired |
| US7132856B2 | Hybrid CVSL pass-gate level-converting sequential circuit for multi-Vcc microprocessors | Electricity | 18 | Expired |
| US6628143B2 | Full-swing source-follower leakage tolerant dynamic logic | Electricity | 18 | Expired |
| US8284766B2 | Multi-core processor and method of communicating across a die | Emerging Cross-Sectional Technologies | 17 | Active |
| US6320795A | Pseudo-static leakage-tolerant register file bit-cell circuit | Physics | 16 | Expired |
| US7800407B1 | Multiple voltage mode pre-charging and selective level shifting | Physics | 15 | Active |
| US10642922B2 | Binary, ternary and bit serial compute-in-memory circuits | Physics | 15 | Active |
| US9035686B1 | Apparatus and method for low power fully-interruptible latches and master-slave flip-flops | Electricity | 15 | Active |
| US7855575B1 | Wide voltage range level shifter with symmetrical switching | Electricity | 14 | Active |
| US7154300B2 | Encoder and decoder circuits for dynamic bus | Electricity | 13 | Expired |
| US7057913B2 | Low-power search line circuit encoding technique for content addressable memories | Physics | 13 | Expired |
| US8577948B2 | Split path multiply accumulate unit | Physics | 13 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.