Method and apparatus for improving the testing, yield and performance of very large scale integrated circuits
US6320803A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 23, 2000 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Mar 23, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
There is provided method and apparatus for improving and making more effective the testing of very large scale integrated (VLSI) devices such as a synchronous random access memory (SDRAM), along with improving their performance and their yield in production. The method includes the steps of providing a VLSI device with switching circuitry which permits respective arrays or banks of the device to be tested alone or simultaneously with separate sequences of test mode signals to identify defects, interactions and unwanted limitations in the overall performance of the device; using the information thus obtained to modify the test mode signals and where indicated the design of the device; iterating the previous steps to optimize a test methodology for the device; and using the optimized test methodology during burn-in of production devices. Logic circuitry is added to a VLSI device to facilitate the improved testing capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.