Apparatus for controlling pipelined memory access requests
US6321233A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 1998 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Dec 15, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99952
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is described for controlling pipelined memory access requests in a computer system. A graphics controller is coupled with a system memory by an AGP interface, which has separate write and read request queues. To control the ordering of the write and read requests relative to one another, each of the requests has an associated age tag assigned to it. In the event a read request is received by the AGP interface, an age tag value is assigned to it that corresponds with the number of previously received and currently pending write requests. Similarly, when a write request is received by the AGP interface, an age tag value is assigned that corresponds with the number of previously received and currently pending read requests. Employing such age tags provides AGP-compliant ordering of the write and read requests, while also providing write-passing-read capability without the attendant complex logic circuitry and time delays associated with conventional implementations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.