Avoiding tag compares during writes in multi-level cache hierarchy
US6321297A · kind A · utility
54Cited by
5References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 5, 1998 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Jan 5, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for avoiding tag compares when writing to a cache. In a cache hierarchy, location information of the cache entries are linked and supplied to the other caches, during caching of the data from memory. When the processor is ready to update the content of the memory location, the location information loaded into a write buffer allows the write buffer to update the cache(s), without the need for tag comparisons to determine if particular entries are present. The avoidance of the tag compare operation during cache update saves a clock cycle, so that overall processor performance is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.