Semiconductor memory system comprising synchronous DRAM and controller thereof
US6321343A · kind A · utility
64Cited by
10References
50Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 27, 2000 |
| Grant date | Nov 20, 2001 |
| Priority date | — |
| Expiry date | Oct 27, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/225
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A maximum flight time measuring circuit constituted by a first delay circuit for delaying a system clock and controlling its delay time in accordance with a strobe clock from DIMMs and a delayline register circuit for storing a delayed state in the delay circuit, and a second delay circuit are provided. Contents of the delayline register circuit are input to the second delay circuit, which is controlled to generate the same delay as that of the first delay circuit. The output of the second delay circuit is supplied as a data fetch signal to a control buffer for receiving read data DQ from the DIMMs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.