Amorphous TFT process
US6323034A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1999 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Aug 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6729
Abstract
A thin film transistor design is described which is not subject to either dark or photo current leakage. The process to manufacture this device begins with the formation of a gate electrode on a transparent substrate followed by its over coating with layers of gate insulation, undoped amorphous silicon, doped amorphous silicon, and a second layer of chromium. The chromium and amorphous silicon layers are then patterned and etched to form a channel pedestal. In a key feature of the invention the vertical side walls of this pedestal are then given a protective coating of oxide or nitride, forming spacers. This is then followed by the deposition of second level metal which is etched to form source and drain electrodes with a suitable gap between them.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.