Intelligent gate-level fill methods for reducing global pattern density effects
US6323113A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1999 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Dec 10, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides methods for intelligently filling a gate layer with dummy fill patterns to produce a target pattern density. A gate layout defining gate areas on the gate layer is provided along with a diffusion layout defining active diffusion areas over a semiconductor substrate. For the gate layout, a pattern density is determined. Then, the areas not occupied by the gate areas and the diffusion areas are determined. Additionally, a range of pattern densities is provided in a set of predefined fill patterns with each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the provided range of pattern densities. Among the set of predefined fill patterns, a predefined fill pattern is selected for producing the target pattern density. Then, the gate layer is filled by placing the dummy fill patterns of the selected predefined fill pattern in the areas not occupied by the gate areas and the diffusion areas. In so doing, the target pattern density is provided in the gate layer when combined with the pattern density of the gate layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.