Method for making silicon nitride-oxide ultra-thin gate insulating layers for submicrometer field effect transistors
US6323143A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 24, 2000 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Mar 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making an improved ultra-thin silicon nitride-oxide gate insulating layer for field effect transistors (FETs) is achieved. After forming a field oxide to electrically isolate device areas on a silicon substrate, an ultra-thin silicon nitride-oxide insulating layer is formed in two process steps. In the first process step a silicon nitride layer is formed on the device areas on the substrate using a low-pressure rapid thermal process (LP-RTP) and a reactant gas of ammonia (NH.sub.3) while insuring that the RTP tool is free of oxygen. Then a second process step is carried out sequentially in the same LP-RTP at an elevated temperature and using an oxygen-rich ambient (dinitrogen oxide N.sub.2 O) as a reoxidation gas. The non-self-limiting characteristic of the ultra-thin-silicon nitride layer results in the controllable diffusion of the dissociated oxygen (O) and nitrous oxide (NO) through the silicon nitride layer to form a thin good quality silicon oxide layer on and in the substrate surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.