Techniques for dicing substrates during integrated circuit fabrication
US6325059A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 8, 1999 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Apr 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/68313
- WIPO fieldOther special machines
- WIPO sectorMechanical engineering
Abstract
The invention relates, in one embodiment, to an arrangement configured to support a substrate during a dicing process. The substrate has thereon a first substrate side and a second substrate side. The first substrate side is smoother than the second substrate side. The arrangement includes a nest having a first nest side and a second nest side. The nest includes a grid which defines at least one nest opening. The nest opening has an opening area that is smaller than an area of a die diced from the substrate. The arrangement further includes a vacuum retainer plate having thereon at least one vacuum pedestal. The vacuum pedestal has an upper surface formed of a resilient material. The vacuum pedestal is configured to be disposed through the nest opening when the nest is mated with the vacuum retainer plate. The vacuum pedestal protrudes above the first nest side of the nest when the vacuum pedestal is disposed through the nest opening from the second nest side to support the substrate on the upper surface and lift the substrate off the first nest side when the substrate is positioned on the nest with the first substrate side facing the first nest side and when the nest is mated with…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.