Programmable logic device with logic signal delay compensated clock network
US6326812A · kind A · utility
45Cited by
6References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 26, 2000 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Jul 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit programmable logic device comprising: a plurality of programmable logic elements that are responsive to clock signals; a clock signal generation circuit which produces a first clock signal; a first phase shifting element which produces a second clock signal which is a phase-shifted version of the first clock signal, shifted in phase by an amount which compensates for a logic signal delay; and a clock signal distribution network which distributes the first and second clock signals among the programmable logic elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.